This invention relates to a semiconductor memory technique and further to a technique particularly useful when applied to a driving system of a read amplification circuit and to a technique useful when applied to a dynamic type RAM (Random Access Memory) requiring a refresh operation, for example.
In a dynamic RAM consisting of charge storage type memory cells, a periodic refresh operation is necessary in order to prevent loss of information resulting from a leakage of the information charge stored in capacitors.
A conventional dynamic RAM incorporates, generally, a refresh controller and selects simultaneously one or several rows of a memory array in accordance with the structure of a memory mat to effect the refresh operation.
A standard 4-mega bit RAM is designed so as to provide a refresh operation 10 to 24 times per 16 ms. Therefore, the number of memory cells to be selected at a time is 4,096 bits. In the DRAM of the type in which the number of memory cells connected to one word line is 1,024 bits, therefore, four word lines are selected simultaneously and in the DRAM in which the number of memory cells on one word line is 2,048 bits, two word lines are selected simultaneously, at the time of refresh.
Such a DRAM is described in Japanese Patent Application No. 195322/1986, for example, published as Japanese Patent Application Laid-open No. 6353786.
Each refresh operation is conducted for read and write or, in other words, in order to read out the information of a memory cell and write again the same information. Therefore, in order to refresh the memory cells of 4,096 bits at a time as described above, at least 4,096 sense amplifiers (read amplification circuits) are necessary.
The conventional dynamic RAM has a construction wherein the number of sense amplifiers which are required during a refresh cycle (4,096 in the 4-M bits DRAM) correspond to the number which are driven simultaneously at the time of ordinary data read-out, too, and desired data is selected from the data read out to the sense amplifiers by a column address, and then amplified and outputted by a main amplifier.
In such a system where all the sense amplifiers determined by the refresh cycle are simultaneously driven, there has been the problem of extremely large power consumption as a result of the charging and discharging of bit lines with the operations of the sense amplifiers.